ECE/CS Distinguished-Speaker Seminar - SPARTA: A Dataflow-Inspired System Design

The Electrical and Computer Engineering department and the Computer Science department will be hosting a seminar featuring Dr. Jean-Luc Gaudiot, IEEE Fellow, Professor of Electrical Engineering and Computer Science at University of California, Irvine. The topic of the seminar will be SPARTA: A Dataflow-Inspired System Design.

Abstract

Computer systems have undergone a fundamental transformation recently, from single-core processors to devices with increasingly higher core counts within a single chip. At the same time, however, more than 10 years ago, Dennard’s scaling came to an abrupt stop, leading to the advent of multi-core chips. Moore’s law is predicted to end in the next 5 years, but it is not yet obvious how, or even whether, the demand for continued growth in performance will continue being satisfied.

To meet some of these challenges, heterogeneity in design, both at the architecture and technology levels, will be the prevailing approach for energy efficient computing as specialized cores, accelerators, etc., can eliminate the energy overheads of general-purpose homogeneous cores. However, with future technological challenges pointing in the direction of on-chip heterogeneity, and because of the traditional difficulty of parallel programming, it becomes imperative to produce new system software stacks that can take advantage of the heterogeneous hardware. As a case in point, the core count per chip continues to increase dramatically while the available on-chip memory per core is only getting marginally bigger. Thus, data locality, already a must-have in high-performance computing, will become even more critical as memory technology progresses. In turn, this makes it crucial that new execution models be developed to better exploit the trends of future heterogeneous computing in many-core chips. To solve these issues, we propose a cross-cutting cross-layer approach to address the challenges posed by future heterogeneous many-core chips.

Speaker Bio

Jean-Luc Gaudiot received the Diplôme d'Ingénieur from ESIEE, Paris, France, in 1976 and the M.S. and Ph.D. degrees in Computer Science from UCLA in 1977 and 1982, respectively. He is currently a Professor in the Electrical Engineering and Computer Science Department at University of California, Irvine. Prior to joining UCI in 2002, he was a Professor of Electrical Engineering at the University of Southern California since 1982. His research interests include multithreaded architectures, fault-tolerant multiprocessors, and implementation of reconfigurable architectures. He has published over 250 journal and conference papers. His research has been sponsored by NSF, DoE, and DARPA, as well as industry. He has served the community in various positions and was just elected to the presidency of the IEEE Computer Society for 2017. He is a Fellow of the IEEE and a Fellow of the AAAS.

Note: If you need more information regarding this seminar, please contact Dr. Jia Wang in ECE, IIT. Phone: 7-3696, Email: jwang@ece.iit.edu